Technical Field
The present invention relates generally to electronic circuits for data communications and other applications.
Description of the Background Art
Several high speed serial protocols, such as the IEEE-1588 standard, the Common Public Radio Interface (CPRI), and PCI Express, require the ability to accurately predict or measure the data bit latency from the package pins to some arbitrary point within a device. Measuring this deterministic latency is needed when synchronization of time is required across different devices in a system or across different systems.
A first-in first-out (FIFO) buffer is commonly used in circuits for data communications and other applications. A write pointer (write counter) is typically used to point to the address in the FIFO buffer where the next word is to be written. Similarly, a read pointer (read counter) is typically used to point to the address in the FIFO buffer from which the next word to be read is obtained.